Call For Papers

The aim of this one-day workshop is to bring together researchers who are interested in optimizing database performance on modern computing infrastructure by designing new data management techniques and tools.

Topics of Interest

The continued evolution of computing hardware and infrastructure imposes new challenges and bottlenecks to program performance. As a result, traditional database architectures that focus solely on I/O optimization increasingly fail to utilize hardware resources efficiently. Multi-core CPUs, GPUs, FPGAs, new memory and storage technologies (such as flash and non-volatile memory), and low-power hardware imposes a great challenge to optimizing database performance. Consequently, exploiting the characteristics of modern hardware has become an important topic of database systems research.

The goal is to make database systems adapt automatically to the sophisticated hardware characteristics, thus maximizing performance transparently to applications. To achieve this goal, the data management community needs interdisciplinary collaboration with computer architecture, compiler, operating systems and storage researchers. This involves rethinking traditional data structures, query processing algorithms, and database software architectures to adapt to the advances in the underlying hardware infrastructure.

We seek submissions bridging the area of database systems to computer architecture, compilers, and operating systems. In particular, submissions covering topics from the following non-exclusive list are encouraged:

• database algorithms and data structures on modern hardware
• cost models and query optimization for novel hierarchical memory systems
• hardware systems for query processing
• data management using co-processors
• novel application of new storage technologies to data management
• query processing using computing power in storage systems
• database architectures for low-power computing and embedded devices
• database architectures on multi-threaded and chip multiprocessors
• performance analysis of database workloads on modern hardware
• compiler and operating systems advances to improve database performance
• new benchmarks for micro-architectural evaluation of database workloads
• taking advantage of modern network capabilities for data processing
• hardware/software co-design for modern data-intensive workloads (e.g., machine learning, graph analytics)

Submission Tracks

We invite submissions to two tracks:

1. Full papers: A full paper must be no longer than 6 pages excluding the bibliography. There is no limit on the length of the bibliography. Full papers describe a complete work in the area of data management for new hardware. Accepted papers will be given 10 pages (plus bibliography) for the camera-ready version and a long presentation slot during the workshop.

2. Short Papers: Short papers must not exceed 2 pages excluding the bibliography. Short papers describe very early stage works or summaries of mature systems. Short papers will be included in the proceedings, given 4 pages (plus bibliography) for the camera-ready version, and may be given a short presentation slot during the workshop.

All accepted papers (full and short) will also be presented as posters during a workshop poster session.

Best of DaMoN 2024

This year all accepted DaMoN papers will be considered for a best paper award.

We intend to invite extended versions of a selection of DaMoN'24 papers for submission to the VLDB Journal. Extended papers that are accepted by the VLDB Journal will appear in a special “Best of DaMoN 2024” section within one of the regular VLDBJ issues.

Important Dates

Paper submission: March 15th, 2024 March 22nd, 2024 (11:59pm PST)

Notification of acceptance: April 26th, 2024 April 29th, 2024

Camera-ready copies: May 10th, 2024 May 15th, 2024 (23:59pm PST)

Workshop: June 10th, 2024

Submission Instructions

Authors are invited to submit original, unpublished research papers that are not being considered for publication in any other forum. Manuscripts should be submitted electronically as PDF files using the latest ACM paper format consistent with the ACM SIGMOD formatting guidelines to the DaMoN 2024 CMT site, at https://cmt3.research.microsoft.com/DaMoN2024. Submissions will be reviewed in a single-blind manner. Submissions that are 2 pages or shorter excluding the bibliography will be reviewed as short papers. Submissions that are 6 pages or shorter excluding the bibliography will be reviewed as full papers. Submissions that are longer than 6 pages excluding the bibliography will be desk-rejected.

Accepted papers will be included within the informal online proceedings at the website. Additionally, all accepted papers will be published online in the ACM Digital Library. Therefore, the papers must include the standard ACM copyright notice on the first page.

Keynote & Invited Talks

Keynote

NVMe and Data Systems: a Decade and Counting

Philippe Bonnet, IT University of Copenhagen

Abstract: NVMe is synonymous with modern storage. It was introduced as a means to efficiently expose Solid-State Drives as PCIe 3.0 peripherals. With NVMe, I/Os were no longer the bottleneck. Initially, the challenge for operating system and database system designers was to accomodate radically faster storage devices. Then, SSDs evolved to meet a range of cost/performance requirements. Accordingly, NVMe 2.0 introduced new transport models, storage models and cross-layer optimizations. This diversity introduced new challenges. Today, NVMe passthru and Flexible Data Placement enable data systems designers to shape how data is stored, instead of designing their systems around the characteristics of opaque storage devices. Computational storage was supposed to further improve the ability of system designers to specialize storage devices to fit their workloads. However, device memory management became a challenge. We discuss the proposed standard and speculate on the role NVMe may play in future data systems, in a context where CXL emerges, PCIe 7.0 is being standardized and power consumption is the bottleneck.

Invited Talks

Computer Architecture in Flux: The Central Processing Unit Is No Longer Central

David Patterson, University of California Berkeley

Abstract: We start with a review of the instability of modern hardware, given the

• slowing of Moore’s Law,
• the end of Dennard scaling, and
• the rise of the demand for AI cycles versus traditional applications.

Data is becoming more critical than compute due to its increasing cost and slowing capacity curves for memory and storage. Data location and movement are now central to cost and performance. To build robust systems in light of these changes, we must shift the focus of hardware and software design from processing to the memory, storage, and network components.

Effortless locality through on-the-fly data transformation

Manos Athanassoulis, Boston University

Abstract: What if we could access any layout and ship only the relevant data through the memory hierarchy by transparently converting rows to (arbitrary groups of) columns? We capitalize on the reinvigorated trend of hardware specialization to propose Relational Fabric, a near-data vertical partitioner that allows memory or storage components to perform on-the-fly transparent data transformation. By exposing an intuitive API, Relational Fabric pushes vertical partitioning to the hardware, which has a profound impact on the process of designing and building data systems. (A) There is no need for data duplication and layout conversion, making hybrid systems viable using a single layout. (B) It simplifies the memory and storage manager. (C) It reduces unnecessary data movement through the memory hierarchy allowing for better hardware utilization and, ultimately, better performance. In this talk, I will introduce the Relational Fabric vision and present our initial results on in-memory systems. I will also share some of the challenges of building this hardware and the opportunities it brings for simplicity and innovation in the data system software stack, including physical design, query processing, and concurrency control, and conclude with ongoing work for data transformation for general workloads including matrix and tensor processing.

Program Committee

Chairs

Carsten Binnig

TU Darmstadt, Germany
carsten.binnig@cs.tu-darmstadt.de

Nesime Tatbul

Intel Labs and MIT, USA
tatbul@csail.mit.edu

Members

• Anastasia Ailamaki, EPFL, Switzerland
• Beng Chin Ooi, National University of Singapore, Singapore
• Danica Porobic, Oracle, Switzerland
• David Cohen, Intel, USA
• Huanchen Zhang, Tsinghua University, China
• Ken Ross, Columbia University, USA
• Lawrence Benson, TU Munich, Germany
• Norman May, SAP SE, Germany
• Orestis Polychroniou, Amazon Web Services, USA
• Pinar Tozun, IT University of Copenhagen, Denmark
• Rathijit Sen, Microsoft, USA
• Rebecca Taft, Cockroach Labs, USA
• Tilmann Rabl, HPI and University of Potsdam, Germany
• Tobias Ziegler, TU Darmstadt, Germany
• Utku Sirin, Harvard University, USA
• Yannis Chronis, Google, USA