Call For Papers

This one-day workshop aims to bring together researchers interested in optimizing database performance on modern computing infrastructure by designing new data management techniques and tools.

Topics of Interest

The continued evolution of computing hardware and infrastructure imposes new challenges and bottlenecks to program performance. As a result, traditional database architectures fail to utilize hardware resources efficiently. Multi-core CPUs, various accelerators (GPUs, FPGAs, etc.), as well as new memory and storage technologies and interconnects provide great opportunities for optimizing database performance. Consequently, exploiting the characteristics of modern hardware has become an essential topic of database systems research.

The goal is to make database systems adapt automatically to sophisticated hardware characteristics, thus maximizing performance transparently for applications. To achieve this goal, the data management community needs interdisciplinary collaboration with researchers from computer architecture, compilers, operating systems, and storage. This involves rethinking traditional data structures, query processing algorithms, and database software architectures to adapt to the advances in the underlying hardware infrastructure.

We seek submissions bridging database systems to computer architecture, compilers, and operating systems. We also invite submissions for papers on hardware/software co-design for modern data-intensive workloads (including, but not limited to machine learning training and inference, graph analytics, and similar tasks). As these workloads continue to grow in scale and complexity, innovative co-design approaches that tightly integrate hardware architectures and software systems are crucial to achieving breakthroughs in performance, energy efficiency, and scalability. In particular, submissions covering topics from the following non-exclusive list are encouraged:

• database algorithms and data structures on modern hardware
• cost models and query optimization for novel hierarchical memory systems
• hardware systems for query processing
• data management using co-processors
• novel application of new storage technologies to data management
• query processing using computing power in network/memory/storage systems
• database architectures for low-power computing and embedded devices
• database architectures on modern tile-based hardware
• performance analysis of database workloads on modern hardware
• compiler and operating systems advances to improve database performance
• new benchmarks for micro-architectural evaluation of database workloads
• taking advantage of modern network/storage/memory capabilities for data processing
• hardware/software co-design for modern data-intensive workloads

Submission Tracks

We invite submissions to two tracks:

1. Full papers: A full paper must be no longer than six pages, excluding the bibliography. There is no limit on the length of the bibliography. Full papers describe a complete work in data management for new hardware. Accepted papers will be given 10 pages (plus a bibliography) for the camera-ready version and a long presentation slot during the workshop.

2. Short Papers: Short papers must not exceed two pages, excluding the bibliography. Short papers describe very early-stage works or summaries of mature systems. Short papers will be included in the proceedings, given 4 pages (plus a bibliography) for the camera-ready version, and may be given a short presentation slot during the workshop.

All accepted papers (full and short) will also be presented as posters during a workshop poster session

Best of DaMoN 2026

This year all accepted DaMoN papers will be considered for a best paper award.

We intend to invite extended versions of a selection of DaMoN'26 papers for submission to the VLDB Journal. Extended papers that are accepted to the VLDB Journal will appear in a special section (“Best of DaMoN 2026”) within one of the regular VLDBJ issues.

Important Dates

Paper submission: February 16th, 2026 February 20th, 2026 (11:59pm AoE)

Notification of acceptance: March 30th, 2026 (11:59pm AoE)

Camera-ready copies: May 1st, 2026

Workshop: Monday June 1st, 2026

Submission Instructions

Authors are invited to submit original, unpublished research papers that are not being considered for publication in any other forum. Manuscripts should be submitted electronically as PDF files using the latest ACM paper format consistent with the ACM SIGMOD formatting guidelines to the DaMoN 2026 CMT site, at https://cmt3.research.microsoft.com/DaMoN2026 (available from February 1st onwards). Submissions will be reviewed in a single-blind manner. Submissions that are longer than six pages, excluding the bibliography, will be desk-rejected.

Accepted papers will be included in the informal online proceedings at the website. Additionally, all accepted papers will be published online in the ACM Digital Library. Therefore, the papers must include the standard ACM copyright notice on the first page.

Keynote & Invited Talks

Keynote Talk

Accelerating Queries at CoddSpeed: Hardware Coprocessors on the Road to Production

Nico Bruno & Matteo Interlandi, Microsoft Jim Gray Labs

Abstract: Modern cloud platforms expose a growing portfolio of specialized hardware — GPUs, FPGAs, DPUs, AI accelerators, etc. — that have the potential to bring substantial speedups to analytical query processing. Ideally, a single generic coprocessor design would let us capture this potential inside a mature commercial database engine: in practice, this is remarkably hard. The real challenges are rarely the kernels themselves: type systems, ANSI semantics, data-layout encodings, hardware availability, and the engineering-process discipline of a production codebase that thousands of customers depend on.

This talk is about CoddSpeed, our effort within the Microsoft Fabric Data Warehouse to build a general substrate for hardware-accelerated query execution that can host different coprocessors over time. We frame the recurring problems any such integration must solve, the architectural decisions we have converged on, and the real-world production surprises that inevitably surface when moving beyond controlled workloads. We ground the talk in our experience with TQP (Tensor Query Processor), a GPU coprocessor whose journey from a research prototype into a system built by 60+ engineers offers a candid case study in what it takes to move accelerator research from the lab to a shipping product. We close with reflections on trust, thoroughness, and concrete strategies for de-risking accelerator research on the road to production.

Fresh Thinking Talk 1

Towards a Programmable Data-Centric AI Stack for Processing-In-Memory Architectures

Christina Giannoula, Max Planck Institute Software Systems

Abstract: Processing-in-Memory (PIM) architectures integrate compute cores close to or within memory arrays, emerging as a promising paradigm to accelerate memory-intensive kernels in modern Machine Learning (ML) models. While ML models contain both compute-intensive and memory-intensive kernels, the latter are often bottlenecked by limited memory bandwidth in conventional CPU and GPU systems. Industry manufacturers and researchers have therefore extensively explored PIM devices and their integration with host CPU/GPU systems to enable efficient end-to-end ML model execution. However, fully leveraging PIM’s benefits for ML applications requires a system software stack that is data-centric and programmable.

This talk explores how specialized libraries, system software, and compilers can unlock the potential of PIM architectures for machine learning workloads. First, I will present PyGim, a novel Graph Neural Network (GNN) library designed specifically for PIM systems, which optimizes memory-intensive GNN kernels through intelligent parallelization strategies. Second, I will introduce DCC, the first data-centric ML compiler for PIM architectures, supporting diverse ML kernels across heterogeneous PIM backends. I will conclude by illustrating that rethinking various stack components to be data-centric and programmable can be the key enabler for the wide adoption of PIM architectures in modern ML systems.

Fresh Thinking Talk 2

Title Coming Soon

Kwanghyun Park, Yonsei University

Abstract: Coming soon

Sponsor Talk

Transparent Huge Pages to the Rescue for In-Memory Data Processing?

Norman May, SAP

Abstract: SAP HANA is known for its high-performance in-memory processing performance, especially for mixed OLAP and OLTP workloads. Hence, it may come as a surprise that SAP HANA did not support transparent huge pages (THP) when using them promises better performance and scalability. In the talk I will present a brief history on our journey towards supporting THP and share some challenges to overcome along the way.

Program Committee

Chairs

Jana Giceva

Technische Universität München, Germany
jana.giceva@in.tum.de

Rathijit Sen

Microsoft Gray Systems Lab
Rathijit.Sen@microsoft.com

Eric Sedlar

Oracle Labs
eric.sedlar@oracle.com

Members

• Azim Afroozeh, CWI, Netherlands
• Anastasia Ailamaki, EPFL, Switzerland
• Beng Chin Ooi, Zhejiang University, China
• Yannis Chronis, ETHZ, Switzerland
• Muhammad El-Hindi, TUM, Germany
• Matteo Interlandi, Microsoft, USA
• Norman May, SAP, Germany
• Kwanghyun Park, Yonsei University, Korea
• Danica Porobic, Oracle, Switzerland
• Kenneth Ross, Columbia University, USA
• Evangelia Sitaridi, NVIDIA, USA
• Nesime Tatbul, Intel Labs and MIT, USA
• Pinar Tözün, IT University of Copenhagen, Denmark
• Tianzheng Wang, Simon Fraser University, Canada
• Huanchen Zhang, Tsinghua University, China

Acknowledgments

The Microsoft CMT service was used for managing the peer-reviewing process for this conference. This service was provided for free by Microsoft and they bore all expenses, including costs for Azure cloud services as well as for software development and support