Call For Papers

This one-day workshop aims to bring together researchers interested in optimizing database performance on modern computing infrastructure by designing new data management techniques and tools.

Topics of Interest

The continued evolution of computing hardware and infrastructure imposes new challenges and bottlenecks to program performance. As a result, traditional database architectures that focus solely on I/O optimization increasingly fail to utilize hardware resources efficiently. Multi-core CPUs, GPUs, FPGAs, new memory and storage technologies (such as flash and non-volatile memory), and low-power hardware imposes a significant challenge to optimizing database performance. Consequently, exploiting the characteristics of modern hardware has become an essential topic of database systems research.

The goal is to make database systems adapt automatically to sophisticated hardware characteristics, thus maximizing performance transparently for applications. To achieve this goal, the data management community needs interdisciplinary collaboration with researchers from computer architecture, compilers, operating systems, and storage. This involves rethinking traditional data structures, query processing algorithms, and database software architectures to adapt to the advances in the underlying hardware infrastructure.

We seek submissions bridging database systems to computer architecture, compilers, and operating systems. We also invite submissions to our call for papers on hardware/software co-design for modern data-intensive workloads, including but not limited to machine learning training and inference, graph analytics, and similar tasks. As these workloads continue to grow in scale and complexity, innovative co-design approaches that tightly integrate hardware architectures and software systems are crucial to achieving breakthroughs in performance, energy efficiency, and scalability. In particular, submissions covering topics from the following non-exclusive list are encouraged:

• database algorithms and data structures on modern hardware
• cost models and query optimization for novel hierarchical memory systems
• hardware systems for query processing
• data management using co-processors
• novel application of new storage technologies to data management
• query processing using computing power in storage systems
• database architectures for low-power computing and embedded devices
• database architectures on multi-threaded and chip multiprocessors
• performance analysis of database workloads on modern hardware
• compiler and operating systems advances to improve database performance
• new benchmarks for micro-architectural evaluation of database workloads
• taking advantage of modern network capabilities for data processing
• hardware/software co-design for modern data-intensive workloads (e.g., machine learning, graph analytics)

Submission Tracks

We invite submissions to two tracks:

1. Full papers: A full paper must be no longer than six pages, excluding the bibliography. There is no limit on the length of the bibliography. Full papers describe a complete work in data management for new hardware. Accepted papers will be given 10 pages (plus a bibliography) for the camera-ready version and a long presentation slot during the workshop.

2. Short Papers: Short papers must not exceed two pages, excluding the bibliography. Short papers describe very early-stage works or summaries of mature systems. Short papers will be included in the proceedings, given 4 pages (plus a bibliography) for the camera-ready version, and may be given a short presentation slot during the workshop.

All accepted papers (full and short) will also be presented as posters during a workshop poster session

Best of DaMoN 2025

This year all accepted DaMoN papers will be considered for a best paper award.

We intend to invite extended versions of a selection of DaMoN'25 papers for submission to the VLDB Journal. Extended papers that are accepted to the VLDB Journal will appear in a special section (“Best of DaMoN 2025”) within one of the regular VLDBJ issues.

Important Dates

Paper submission: March 14th, 2025 March 21st, 2025 (11:59pm AoE)

Notification of acceptance: April 28th, 2025

Camera-ready copies: May 23rd, 2025

Workshop: June 23rd, 2025

Submission Instructions

Authors are invited to submit original, unpublished research papers that are not being considered for publication in any other forum. Manuscripts should be submitted electronically as PDF files using the latest ACM paper format consistent with the ACM SIGMOD formatting guidelines to the DaMoN 2025 CMT site at https://cmt3.research.microsoft.com/DaMoN2025 (available from mid-February on). Submissions will be reviewed in a single-blind manner. Submissions that are two pages or shorter, excluding the bibliography, will be reviewed as short papers. Submissions that are six pages or shorter, excluding the bibliography, will be reviewed as full papers. Submissions that are longer than six pages, excluding the bibliography, will be desk-rejected.

Accepted papers will be included in the informal online proceedings at the website. Additionally, all accepted papers will be published online in the ACM Digital Library. Therefore, the papers must include the standard ACM copyright notice on the first page.

Keynote & Invited Talks

Keynote Talk

Building Portable, Low-Latency Query Compilers

Thomas Neumann, TU Munich

Abstract: Compiling SQL queries into native machine code is appealing due to the elimination of interpretation overhead and the potential for highly efficient execution. However, there are concerns regarding code complexity, compilation time, and portability across hardware platforms. In this talk, we will demonstrate that it is possible to build a low-latency query compiler by factoring out the complex components, implementing them only once. The platform-specific components are then relatively straightforward, facilitating the targeting of new hardware platforms. Compared to traditional compiler backends, this approach achieves nearly the same execution speed while significantly reducing compilation times, thereby greatly improving overall query latency.

Fresh Thinking Talk

The Power of an Instruction

Michal Friedman, ETH Zurich

Abstract: Over the past few decades, the evolution of instructions, serving as the primary interface exposed by new hardware architectures, has significantly influenced how we write and optimize software. These instructions have even become so deeply embedded in libraries and abstractions that they are often invisible to the typical programmer.

Yet, selecting and leveraging the right instructions can have a substantial impact on both performance and correctness of the systems built on top of them. In this talk, I will explore the influence of modern instruction set extensions such as AVX for vectorized computation, CLFLUSH for cache management, and PREFETCH for reducing memory latency, and how they shape algorithm design, data layout and system behaviour.

Furthermore, I will outline potential advancements including mechanisms like eliminating redundant cache flushes and introducing multi-word compare-and-swap operations. We will explore how such extensions could simplify synchronization and reduce overhead, particularly in disaggregated and high-concurrency environments. These proposals aim to push the boundaries of what low-level primitives can offer, demonstrating how the smallest units of computation can impact on how we design and reason about modern systems.

Industry Talk

Title Coming Soon

Carlo Curino, Microsoft Jim Gray Labs

Abstract: Coming soon

Sponsor Talk

Improving the Performance of the Vector Engine Index in SAP HANA

SAP

Abstract: SAP HANA Cloud features a Vector Engine for use in Retrieval-Augmented Generation (RAG) to improve the quality of response of AI-powered business applications using external knowledge. We share results of the micro-architectural analysis of the index construction time. Based on this analysis we share how tuning the code significantly improved the performance of index construction. Key to these improvements were NUMA optimizations and harnessing the memory prefetcher of modern Intel CPUs.

Program Committee

Chairs

Carsten Binnig

TU Darmstadt, Germany
carsten.binnig@cs.tu-darmstadt.de

Eric Sedlar

Oracle Labs
eric.sedlar@oracle.com

Members

• Anastasia Ailamaki, EPFL, Switzerland
• Yannis Chronis, Google, USA
• Muhammad El-Hindi, Technische Universität Darmstadt, Germany
• Jana Giceva, Technische Universität München, Germany
• Norman May, SAP SE, Germany
• Beng Chin Ooi, National University of Singapore, Singapore
• Orestis Polychroniou, Amazon Web Services, USA
• Danica Porobic, Oracle, Switzerland
• Tilmann Rabl, Hasso Plattner Institute/ University of Potsdam, Germany
• Kenneth Ross, Columbia University, USA
• Rathijit Sen, Microsoft, USA
• Utku Sirin, Harvard University, USA
• Rebecca Taft, Cockroach Labs, USA
• Pinar Tozun, IT University of Copenhagen, Denmark
• Tianzheng Wang, Simon Fraser University, Canada
• Huanchen Zhang, Tsinghua University, China
• Tobias Ziegler, Technische Universität München, Germany